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this is information on a product in full production. september 2012 doc id 022927 rev 3 1/43 43 stcf04 high power white led supercap? driver with i2c interface datasheet ? production data features buck-boost converter with 1.5 a peak current limiting and synchronous rectification burst mode operation when output is charged input voltage range 2.5 v to 5.5 v programmable output charging voltage up to 5.5 v full i2c control operation modes: ? shutdown mode ? monitoring mode with ntc and supercap monitoring ? idle mode ?flash mode ? torch mode: up to 320 ma controlled led current in all modes soft and hard triggering of flash, torch and picture light modes torch dimming in 12 exponential steps flash dimming in 8 steps active balancing of supercap voltage supercap status flag internally or externally timed flash operation digitally programmable safety timeout in flash mode torch mode safety timeout led overtemperature detection and protection with external ntc resistor shorted led failure detection and protection chip overtemperature detection and protection applications cell phones and smartphones camera flashes/strobe pdas and digital still cameras description the stcf04 is a dedicated and space optimized high efficiency solution for driving a flash led module in cameras, phones, pdas and other handheld devices using the supercap technology. it is based on a dc-dc buck-boost converter, which ensures a proper and efficient charging control and monitoring of the supercap in the whole battery voltage range. the output current control ensures a good current regulation over the forward voltage spread characteristics of the flash leds in torch and flash mode operation. the supercap charging current is limited to a defined value which avoids overload of the battery. the supercap discharge current flows through the leds and the external mosfet which must be chosen according to the desired flash current. tfbga25 (3 x 3 mm) table 1. device summary order code package packaging STCF04TBR tfbga25 (3 x 3 mm) 3000 parts per reel www.st.com
contents stcf04 2/43 doc id 022927 rev 3 contents 1 description (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8 detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.1 logic pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.1.1 scl, sda pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.1.2 flash pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.1.3 torch pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.1.4 reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.1.5 atn pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.1.6 add pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.1.7 ready pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.1.8 data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.1.9 start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.1.10 byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.1.11 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.1.12 interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.1.13 writing to a single register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.1.14 writing to multiple registers with incremental addressing . . . . . . . . . . . 20 8.1.15 reading from a single register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.1.16 reading from multiple registers with incremental addressing . . . . . . . . 21 9 description of the internal registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.1 commands (cmd_reg) 00(hex) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
stcf04 contents doc id 022927 rev 3 3/43 9.1.1 pwr_on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.1.2 flash_on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.1.3 tch_on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.1.4 ntc_on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.1.5 tchv_h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.1.6 chrg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.1.7 montr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.2 flash register (fl_reg) 01(hex) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.3 aux led (aux_reg) 02(hex) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.4 status (stat_reg) 03(hex) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9.5 feature (ftr_reg) 04(hex) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9.6 torch register (trch_reg) 05(hex) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10 theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.1 the state machine diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.2 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 10.2.1 reset pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 10.3 shutdown mode and ntc mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 10.4 monitoring mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 10.5 idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 10.6 aux led . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 10.7 single or multiple flash using external (microprocessor) temporization . . 30 10.8 external (microprocessor) temporization using the flash_on bit . . . . . 31 10.9 single flash using internal temporization . . . . . . . . . . . . . . . . . . . . . . . . . 31 10.10 light sensor feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 11 typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 12 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 13 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
list of tables stcf04 4/43 doc id 022927 rev 3 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 4. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 5. list of external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 6. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 7. i2c address table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 8. interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 9. i2c register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 10. command register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 11. flash register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 12. flash mode dimming registers settings (ext_reg = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 13. flash time dimming register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 14. aux led register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 15. auxiliary led dimming table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 16. auxiliary led timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 17. status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 18. status register details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 19. feature register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 20. light sensor reference dimming register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 21. dc-dc converter output voltages (v out ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 22. dc-dc converter coil peak current limit values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 23. torch register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 24. torch mode dimming registers settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 25. the safety timeout for torch mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 26. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
stcf04 list of figures doc id 022927 rev 3 5/43 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 4. behavior of the ready pin in different modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 5. data validity on the i2c bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 6. timing diagram on i2c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 7. bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 8. acknowledge on i2c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 9. writing to a single register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 10. writing to multiple registers with incremental addressing . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 11. reading from a single register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 12. reading from multiple registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 13. state machine diagram of the stcf04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 14. reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 15. flash current vs. input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 16. torch current vs. input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 17. aux led current vs. input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 18. charging efficiency vs. v out voltage (v in = 3.6 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 19. torch time - settings compared to real values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 20. torch current - settings compared to real values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 21. flash time - settings compared to real values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 22. flash current - settings compared to real values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 23. aux led time - settings compared to real values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 24. aux led current- settings compared to real values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 25. operation in flash mode - single flash pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 26. operation in flash mode - multiple flash pulses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 27. operation in torch mode with tchv_h bit = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 28. operation in torch mode with tchv_h bit = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
description (continued) stcf04 6/43 doc id 022927 rev 3 1 description (continued) all the functions of the device are controlled through the i2c bus which reduces the number of logic pins of the package and saves pcb tracks on the application board. hard and soft- triggering of flash and torch are both supported. the device includes many functions to protect the chip and the power leds. these include a soft-start control, chip overtemperature detection and protection, and shorted led detection and protection. in addition, a digital programmable timeout function protects the leds in case of a wrong command issued by the microprocessor. an optional external ntc is supported to protect the leds against overheating. it is possible to separately program the current intensity in flash and torch mode through i2c. in order to guarantee the proper function of flash mode, the supercap voltage should be monitored by the microprocessor using the ready pin feature. in case of insufficient power from the supercap, a warning is generated. the device is packaged in bga 3 x 3 mm with 1 mm height.
stcf04 diagram doc id 022927 rev 3 7/43 2 diagram figure 1. block diagram torch dimming torch dimming control logic prereg & bias i 2 c interf oscillator & time counter protections & diagnostics ntc bias on - chip temp over - current ntc_on led led fail + - + - ref4 ref5 vlx1 ready atn scl sda add ntc rx pgnd agnd ntc_on ntc_h ntc_w buck converter vmid supercap balancing & voltage control supercap balancing & voltage control pgnd isens flash triggering ¤t limititing flash triggering ¤t limititing current sensing lsin lscon drive auxled torch flash vbat reset pvbat vlx2 boost converter vout auxled enable/ 1.8 v ref mx mx ref 120 mv..1.2 v torch dimming torch dimming control logic prereg & bias i 2 c interf oscillator & time counter protections & diagnostics ntc bias on - chip temp over - current ntc_on led led fail + - + - ref4 ref5 vlx1 ready atn scl sda add ntc rx pgnd agnd ntc_on ntc_h ntc_w buck converter vmid supercap balancing & voltage control supercap balancing & voltage control pgnd isens flash triggering ¤t limititing flash triggering ¤t limititing current sensing lsin lscon drive auxled torch flash vbat reset pvbat vlx2 boost converter vout auxled enable/ 1.8 v ref mx mx ref 120 mv..1.2 v
pin configuration stcf04 8/43 doc id 022927 rev 3 3 pin configuration figure 2. pin connection (top view) table 2. pin description pin symbol description a1 vlx1 inductor connection 1 e1 vlx2 inductor connection 2 d5 r x r x resistor connection d1 vout supercap connection c1 vmid supercap middle pin connection e5 ntc ntc resistor connection a3 ready supercap status flag pin b3 scl i2c clock signal a4 flash flash trigger input e2 agnd signal ground b5 torch torch trigger input b4 reset external reset input d4 isens flash regulator sensing connection c3 add i2c address selection e4 led diode module cathode connection c4 atn attention (open drain output, active low) b1 pvbat supply voltage a5 sda i2c data e3 auxled auxiliary red led connection b2 lscon light sensor capacitor connection d3 vbat signal supply voltage a2 lsin light sensor input c5 drive mosfet driver output c2, d2 pgnd power ground + die back connection
stcf04 maximum ratings doc id 022927 rev 3 9/43 4 maximum ratings note: absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. table 3. absolute maximum ratings symbol parameter value unit vbat, pvbat signal supply voltage - 0.3 to 6 v vlx inductor connection - 0.3 to 6 v vout supercap connection - 0.3 to 6 v vdcdc dc-dc converter output - 0.3 to 6 v vmid supercap middle pin connection - 0.3 to 6 v auxled auxled connection - 0.3 to 6 v led led connection - 0.3 to 6 v scl, sda, atn, add, ready, torch, flash, reset logic pins - 0.3 to v bat + 0.3 v pvbat power supply voltage - 0.3 to v bat + 0.3 v drive external mosfet drive - 0.3 to 6 v lsin light sensor input - 0.3 to 6 v lscon light sensor capacitor connection - 0.3 to 6 v r x connection for reference resistor - 0.3 to 3 v ntc connection for led temperature sensing - 0.3 to 3 v isens flash regulator sensing connection - 0.3 to 3 v esd human body model 2kv p tot continuous power dissipation (at t a =70 c) 1 w t op operating junction temperature range - 40 to 85 c t j junction temperature - 40 to 150 c t stg storage temperature range - 65 to 150 c table 4. thermal data symbol parameter value unit r thja thermal resistance junction-ambient (1) 56 c/w 1. this parameter corresponds to the pcb board, 8 layers with 1 inch2 of cooling area.
application stcf04 10/43 doc id 022927 rev 3 5 application figure 3. application schematic note: **: connect to v i , or gnd or sda or scl to choose one of the 4 different i2c slave addresses. optional components to support auxiliary functions are highlighted with blue rectangles. note: the anode of the auxled should be also connected to the v out .
stcf04 application doc id 022927 rev 3 11/43 note: the components listed above refer to a typical application. however, stcf04 operation is not limited to the choice of these external components. table 5. list of external components component manufacturer part number value size l murata lqm2hpn1r0mjc 1 h / 1.5 a 2.5 x 2.0 x 1.1 mm tdk vls252012t-1r0n1r7 1 h / 1.7 a 2.5 x 2.0 x 1.2 mm cin, cout tdk c1608x5r0j106mt 10 f / 6.3 v 0603 rx rohm mcr01mzpj15k 15 k 0402 ntc murata ncp21wf104j03ra 100 k 0805 csup murata dme2w5r5k404m 400 mf / 5.5 v 20.5 x 18.5 x 3 mm tdk edlc152344 550 mf / 5.5 v 44 x 23 x 1.5 mm edlc272020 500 mf / 5.5 v 20 x 20 x 2.7 mm cap-xx gs 2 19f 1.6 f / 5 v 40 x 17 mm led module luxeon 4x lxcl-pwf4 white led 0805 t fl stmicroelectronics stl8nh3ll 8 a / 12 m 3.3 x 3.3 x 0.9 mm r fl tyco tl2br01fte 0r01 1206 c int (1) tdk 10 f / 6.3 v 0402 r light * tyco 0402 t foto * vishay temt6000 4 x 2 x 1 mm auxled red led 0603 c r 100 nf 0402 1. optional components for the auxiliary light sensor feature.
electrical characteristics stcf04 12/43 doc id 022927 rev 3 6 electrical characteristics t a = 25 c, v in = 3.6 v connected to v bat and p vbat , c in = 10 f, c sup = 1.6f/5 v l = 1 h, r x = 15 k , v fled = 4.2 v/10 a. unless otherwise specified, typical values are at 25 c. table 6. electrical characteristics symbol parameter test conditions min. typ. max. unit v in operating input supply voltage 2.5 5.5 v v pw_on reset power-on reset threshold v in rising 2.3 v i o output current adjustment range i torch torch mode v in =2.7 v to 5.5 v 15 320 ma auxiliary led output current adjustment range i auxled idle mode, v i or v o =3.3 v to 5.5 v 0 100 v isens current sensing input v in =2.7 v to 5.5 v, i led = 12 a r fl = 10 m 108 120 132 mv i peak switch peak current limit v in =2.7 v to 5.5 v, idc0=0 1.45 a v in =2.7 v to 5.5 v, idc0=1 1.80 v out regulated voltage range optimized for flash mode v in =2.7 v to 5.5 v 4.5 5.5 v regulated voltage range optimized for torch mode v in =2.7 v to 5.5 v v fled + 0.25 v v out tolerance percentage with respect to programmed voltage -5 +5 % i mid active balancing output v in =2.7 v to 5.5 v -400 400 ma i o output current variation torch mode i led = 300 ma -10 10 % i q quiescent current in shutdown mode v in =2.7 to 5.5 v, ntc_on=0 1 a quiescent current in shutdown mode v in =2.7 to 5.5 v, ntc_on=1 2 quiescent current in monitoring mode ntc_on=0, supercap monitoring=1 45 quiescent current in idle mode ntc_on, chrg=0 1 ma f s switching frequency v in =2.7 v 1.8 mhz
stcf04 electrical characteristics doc id 022927 rev 3 13/43 symbol parameter test conditions min. typ. max. unit efficiency of the converter v in =3.7 v, vdc_0,1=1, idc0=1 85 % efficiency in torch mode operation v in =2.7 v to 4.2 v, idc_0=1, tchv_h=1 i torch =320 ma 50 v in =2.7 v to 4.2 v, idc_0=1, tchv_h=0 i torch =320 ma 70 v suphyst supercap regulated voltage hysteresis v supmax =5.5 v, v supmin =5.5 v- v suphyst, tchv_h=1 or flash_on=1 1.3 v v supmax =5.0 v, v supmin =5.0 v- v suphyst, tchv_h=1 or flash_on=1 0.8 v supmax =4.5 v, v supmin =4.5 v- v suphyst , tchv_h=1 or flash_on=1 0.3 v supmax =4.2 v, v supmin =4.2 v- v suphyst , tchv_h=0 0.2 v moniready supercap voltage ready hysteresis pwr_on=0, vdc_0 or/and vdc_1=1 0.2 v otp overtemperature protection v in =5.5 v 140 c othyst overtemperature hysteresis v in =5.5 v 20 c v_ntcw ntc threshold warning idle mode, i ntc =2 ma max. 0.56 v v_ntch ntc threshold hot idle mode, i ntc =2 ma max. 1.2 v vol output logic signal level low atn, ready i atn, ready =+10 ma 0.3 v i oz output logic leakage current atn, ready v atn, ready =3.3 v 1 ma v il input logic signal level scl, sda, test, reset, schrg, flash, torch, add v in =2.7 v to 5.5 v 00.4 v v ih 1.4 3.0 i lscon input reset current v in =2.7 v to 5.5 v, v ref =1.6 v 10 ma v lsin analog input signal range v in =2.7 v to 5.5 v 0.1 1.6 v v drive mosfet driver output source: i drive = -8 ma 4.27 v sink: i drive = +8 ma 1.05 v reference voltage range ext_reg=1 (1) 0.12 1.2 v t on led current rise time i led =0 to i led =max. flash triggered by external trig 0.3 ms table 6. electrical characteristics (continued)
electrical characteristics stcf04 14/43 doc id 022927 rev 3 symbol parameter test conditions min. typ. max. unit t resmin minimum reset time v in =2.7 v to 5.5 v 1 s t lscapres reset time of the light sensor capacitor 200 s table 6. electrical characteristics (continued)
stcf04 introduction doc id 022927 rev 3 15/43 7 introduction the stcf04 is a high efficiency buck-boost converter with input current limitation dedicated to managing the power for flash/torch mode operations using the supercap technology and to control the high current white leds in cell phone cameras and portable applications in general. the device operates in free-running mode with a coil peak current limiter. it charges and stores the energy on the supercap from a single cell lithium-ion battery (2.5 v to 4.2 v). the device contains an active balancer circuit able to regulate the middle pin of the supercap, therefore guaranteeing the reliability of the supercap component. the device operation and diagnostic are controlled by the i2c bus. torch current is adjustable from 15 ma to 320 ma. the maximum flash current is set by choosing the r fl resistor and it can be adjusted by i2c using a dedicated register. the device operates as a standalone flash supercap controller able to drive one external mosfet. the device has two modes of managing the energy in the supercap during torch mode operation, both adjustable by i2c: 1. torch mode 1: in this case the output current in torch mode is regulated from v out, which is set by v dc bits in the feature register (r4). this mode is optimized to give the possibility of triggering the flash without any delay caused by a recharging of the supercap. 2. torch mode 2: in this case the output current in torch mode is regulated from v out = v fled + 0.25 v. this mode is optimized for maximum efficiency in torch mode. the supercap must be recharged after the end of torch mode operation. the device uses an external ntc resistor to sense the temperature of the white leds and light sensor management to optimize the flash duration in flash mode. these last two functions are optional so they may not be needed in all applications, and, in such cases, the relevant external components can be omitted. in monitoring mode, when the voltage monitoring mode of the supercap is active, the device is working with low consumption. when the ready pin goes high, meaning that the supercap has been self-discharged, the p should initiate a re-charge of the supercap, for example, by entering charge mode.
detailed description stcf04 16/43 doc id 022927 rev 3 8 detailed description 8.1 logic pins 8.1.1 scl, sda pins these are the standard clock and data pins as defined in the i2c bus specifications. external pull-ups are required according to i2c bus specifications. 8.1.2 flash pin this input pin is internally and-ed with the flash_on bit to generate the internal signal that activates the flash operation. this gives the user the possibility to accurately control the flash duration using a dedicated pin, avoiding the i2c bus latencies (hard-triggering). neither internal pull-up nor pull-down is provided. 8.1.3 torch pin this input pin is internally and-ed with the tch_on bit to generate the internal signal that activates the torch operation. neither internal pull-up nor pull-down is provided. 8.1.4 reset pin this pin works as an external reset input. the microprocessor can use this pin to reset the stcf04 at any time. neither internal pull-up nor pull-down is provided. this pin is active low. 8.1.5 atn pin this output pin (open drain, active low) is provided to better manage the information transfer from the stcf04 to the microprocessor. because of the limitations of a single master i2c bus configuration, the microprocessor should regularly communicate with the stcf04 to verify if certain operations have been completed, or to check diagnostic information. alternatively, the microprocessor can use the atn pin to be advised that a new data is available in the stat_reg register, therefore avoiding continuous communication. the information may then be read in the stat_reg by a read operation via i2c which also automatically resets the atn pin to high. the stat_reg is also reset to 0. no internal pull-up is provided. 8.1.6 add pin this pin offers the opportunity of selecting one of the 4 possible i2c slave addresses. neither internal pull-up nor pull-down is provided. the pin must be connected to gnd, vbat, scl or sda to select the desired i2c slave address (see ta b l e 7 ). this pin cannot be left floating.
stcf04 detailed description doc id 022927 rev 3 17/43 8.1.7 ready pin this pin can be used to monitor the voltage on the supercap by the microprocessor. the status of this pin has different meanings according to the current mode of operation of the stcf04. - idle, monitoring, torch mode with tchv_h=1: the ready pin goes low when the supercap voltage reaches the threshold voltage set by the v dc register, otherwise the ready pin is high when v supercap goes below v dc voltage - 0.2 v of hysteresis. when ready is high it means that it is necessary to recharge the supercap in order to be able to make a flash. - torch mode with tchv_h=0: the ready pin goes low when the supercap reaches 4.2 v and is high when the supercap is below 4.2 v and torch mode is not active. - flash: the ready pin goes low as soon as the supercap voltage reaches the threshold voltage set by the v dc register. it stays low until the supercap voltage decreases below 4.2 v and flash mode is not active. this feature allows the user to perform multiple flashes. see figure 4 below for details. figure 4. behavior of the ready pin in different modes table 7. i2c address table add pina7a6a5a4a3a2a1a0 gnd0110000r/w vbat0110001r/w sda0110010r/w scl0110011r/w
detailed description stcf04 18/43 doc id 022927 rev 3 data transmission from the main microprocessor to the stcf04 and vice versa takes place through the 2 i2c bus interface wires, consisting of the two lines sda and scl (pull-up resistors to a positive supply voltage must be externally connected). 8.1.8 data validity as shown in figure 5 , the data on the sda line must be stable during the high period of the clock. the high and low state of the data line can only change when the clock signal on the scl line is low. 8.1.9 start and stop conditions both data and clock lines remain high when the bus is not busy. as shown in figure 6 , a start condition is a high to low transition of the sda line while scl is high. the stop condition is a low to high transition of the sda line while scl is high. a stop condition must be sent before each start condition. figure 5. data validity on the i2c bus cs11340 figure 6. timing diagram on i2c bus
stcf04 detailed description doc id 022927 rev 3 19/43 8.1.10 byte format every byte transferred to the sda line must contain 8 bits. each byte must be followed by an acknowledge bit. the msb is transferred first. one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse. any change in the sda line at this time is interpreted as a control signal. figure 7. bit transfer 8.1.11 acknowledge the master (microprocessor) puts a resistive high level on the sda line during the acknowledge clock pulse (see figure 8 ). the peripheral (stcf04) that acknowledges must pull down (low) the sda line during the acknowledge clock pulse, so that the sda line is stable low during this clock pulse. the peripheral which has been addressed must generate an acknowledge pulse after the reception of each byte, otherwise the sda line remains at the high level during the ninth clock pulse duration. in this case, the master transmitter can generate the stop information in order to abort the transfer. the stcf04 does not generate the acknowledge bit if the v i supply is below 2.7 v. figure 8. acknowledge on i2c bus 8.1.12 interface protocol the interface protocol is composed of ( ta bl e 8 ): - a start condition (start) - a device address + r/w bit (read =1 / write =0) - a register address byte am11867v1
detailed description stcf04 20/43 doc id 022927 rev 3 - a sequence of data n* (1 byte + acknowledge) - a stop condition (stop) the register address byte determines the first register in which the read or write operation takes place. when the read or write operation is finished, the register address is automatically incremented. 8.1.13 writing to a single register writing to a single register starts with a start bit followed by the 7-bit device address of the stcf04. the 8 th bit is the r/w bit, which is 0 in this case. r/w = 1 means a reading operation. the master then waits for an acknowledgement from the stcf04. the 8-bit register address is then sent to the stcf04. it is also followed by an acknowledge pulse. the last transmitted byte is the data to be written to the register. it is again followed by an acknowledge pulse from the stcf04. the master then generates a stop bit and the communication is over. see figure 9 below. figure 9. writing to a single register 8.1.14 writing to multiple regi sters with incremental addressing it would be impractical to send the device address and the address of the register when writing to multiple registers several times. the stcf04 supports writing to multiple registers with incremental addressing. when data is written to a register, the address register is automatically incremented, so the next data can be sent without sending the device address and the register address again. see figure 10 below. table 8. interface protocol device address + r/w bit register address data 76543210 76543210 76543210 s t a r t m s b l s b r w a c k m s b l s b a c k m s b l s b a c k s t o p s t a r t device addre ss 7 bit s a c k w r i t e m s b l s b r / w a c k addre ss of regi s ter data a c k a c k s t o p m s b m s b l s b l s b s da line am11 8 6 3 v1
stcf04 detailed description doc id 022927 rev 3 21/43 8.1.15 reading from a single register the reading operation starts with a start bit followed by the 7-bit device address of the stcf04. the 8 th bit is the r/w bit, which is 0 in this case. the stcf04 confirms receipt of the address + r/w bit by an acknowledge pulse. the address of the register that should be read is sent afterwards and confirmed again by an acknowledge pulse of the stcf04 again. then the master generates a start bit again and sends the device address followed by the r/w bit, which is now 1. the stcf04 confirms receipt of the address + r/w bit by an acknowledge pulse and starts to send the data to the master. no acknowledge pulse from the master is required after receiving the data. then the master generates a stop bit to terminate the communication. see figure 11 . 8.1.16 reading from multiple regi sters with incremental addressing reading from multiple registers starts in the same way as reading from a single register. as soon as the first register is read, the register address is automatically incremented. if the master generates an acknowledge pulse after receiving the data from the first register, then reading of the next register can start immediately without sending the device address and the register address again. the last acknowledge pulse before the stop bit is not required. see figure 12 . figure 10. writing to multiple registers with incremental addressing am11 8 64v1 s t a r t d evic e addre ss 7 bit s a c k w r i t e m s b l s b r / w a c k addre ss of regi s ter i data i a c k a c k s t o p m s b m s b l s b l s b data i +1 a c k l s b d a ta i +2 a c k l s b d a ta i+2 l s b d a ta i +n a c k m s b m s b m s b m s b m s b a c k l s b s da line figure 11. reading from a single register am11 8 65v1 s t a r t d evic e addre ss 7 bit s a c k w r i t e m s b l s b r / w addre ss of regi s ter a c k m s b l s b s t a r t a c k r / w r e a d d evic e addre ss 7 bit s data l s b s t o p n o a c k s da line
detailed description stcf04 22/43 doc id 022927 rev 3 figure 12. reading from multiple registers am11 8 66v1 s t a r t d evic e addre ss 7 bit s a c k w r i t e m s b l s b r / w addre ss of regi s ter i a c k m s b l s b s t a r t a c k r / w r e a d device addre ss 7 bit s data i a c k s t o p l s b d a ta i +1 a c k l s b d a ta i +2 a c k l s b data i+2 l s b data i +n m s b m s b m s b m s b a c k l s b n o a c k s da line
stcf04 description of the internal registers doc id 022927 rev 3 23/43 9 description of the internal registers note: all the registers can be read only when the pwr_on bit is 1. reading any register when pwr_on = 0, gives 0 regardless of the real value of the register. this concerns command and feature registers in monitoring mode and shutdown + ntc mode. 9.1 commands (cmd_reg) 00(hex) 9.1.1 pwr_on when set, it activates all analog and power internal blocks including the ntc supporting circuit, and the device is ready to operate (idle mode). as long as pwr_on=0, only the i2c interface is active, minimizing shutdown mode power consumption. 9.1.2 flash_on this bit is and-ed with the flash pin to generate the internal signal fl_on that activates flash mode. in this way, both soft-triggering and hard-triggering of the flash are possible. if soft-triggering (through i2c) is chosen, the flash pin is not used and must be kept high (tied to vbat). if hard-triggering is chosen, then the flash pin must be connected to a microprocessor i/o devoted to flash timing control, and the flash_on bit must be set in advance. both triggering modes can benefit from the internal flash time counter, which uses the flash_on bit and can work either as a safety shutdown timer or as a flash duration timer. flash mode can start only if pwr_on=1. the led current is controlled by the value set by the fdim_0~2 of the dim_reg. 9.1.3 tch_on torch on: when set to 1 from idle mode, the stcf04 enters torch mode. the led current is controlled by the value set by the tdim_0~3 of the torch_reg. table 9. i2c register mapping register name sub address (hex) operation description cmd_reg 00 r / w commands fl_reg 01 r / w flash register aux_reg 02 r / w auxiliary led stat_reg 03 r only status register ftr_reg 04 r / w features trch_reg 05 r / w torch register table 10. command register cmd_reg (write mode) msb lsb sub add=00 pwr_on flash_on tch_on ntc_on tchv_h chrg montr n/a power-on reset value 0 0 00000 0
description of the internal registers stcf04 24/43 doc id 022927 rev 3 9.1.4 ntc_on this bit activates the comparators that monitor the led temperature. ntc-related blocks are always active regardless of this bit in torch mode and flash mode. 9.1.5 tchv_h torch voltage high: when set to 1, the supercap voltage is maintained to the value set by the feature register (vdc_0~1) during torch mode. if this bit is set to 0, voltage on the supercap is regulated to maintain the desired torch current and optimize the efficiency in torch mode. 9.1.6 chrg this bit enables the charging of the supercap, when set to 1, the device starts to charge the supercap by the limited current from the pvbat. during this operation the active balancing circuit is enabled. 9.1.7 montr when this bit is set and the vdc voltage in the feature register is set to a non-zero value at the same time, the device enters monitoring mode. 9.2 flash register (fl_reg) 01(hex) fdim_0~2: these 3 bits define the led current in flash mode with 8 values. ftim_0~4: these 5 bits define the flash duration timer value in flash mode with 32 values. note: r fl is the external sensing resistor, external mos transistor connected, see figure 3 . table 11. flash register cl_reg (write mode) msb lsb sub add=01 ftim_4 ftim_3 ftim_2 ftim_1 ftim_0 fdim_2 fdim_1 fdim_0 power-on, shutdown mode reset value 00000000 table 12. flash mode dimming registers settings (ext_reg = 0) f_dim (hex)01234567 drive voltage [mv]** 12 48 60 72 84 96 108 120 led current [a]* 0.012 v / r fl 0.048 v / r fl 0.060 v / r fl 0.072 v / r fl 0.084 v / r fl 0.096 v / r fl 0.108 v / r fl 0.120 v / r fl example led current (a) for r fl = 10 m 1.2 4.8 6 7.2 8.4 9.6 10.8 12
stcf04 description of the internal registers doc id 022927 rev 3 25/43 ftim_0~4 : these 5 bits define the maximum flash duration. it is intended to limit the energy dissipated by the led to a maximum safe value or to leave the control of the flash duration to the stcf04 during normal operation. values from 0~31 correspond to 0~410 ms (according to ta b l e 1 3 ). the timing accuracy is related to the internal oscillator frequency that clocks the flash time counter (+/- 20%). entering flash mode (either by soft or hard triggering) activates the flash time counter, which begins counting down from the value loaded in the f_tim register. when the counter reaches zero, flash mode is stopped by resetting the trig_en bit, and simultaneously, the atn pin is set to true (low) to alert the microprocessor that the maximum time has been reached. the ftim value remains unaltered at the end of the count. 9.3 aux led (aux_reg) 02(hex) auxi_0~3 : this 4-bit register defines the aux led current from 0 to 100 ma. see ta b l e 1 5 aux led dimming for reference. loading any value between 1 and 11 also starts the aux led current source timer, if enabled. the aux led current source is active only in idle mode, and is deactivated in any other mode. auxt_0~3 : this 4-bit register controls the timer that defines the on-time of the aux led current source. on-time starts when the auxi register is loaded with any value other than zero, and stops after the time defined in the auxt register. values from 0 to 14 of the auxt register correspond to an on-time of the aux led ranging from 100 to 1500 ms in 100 ms steps. the value 15 puts the aux led into the continuous light mode. the activation/deactivation of the aux led current source is controlled using only the auxi register. table 13. flash time dimming register settings ftim_dim(hex)0123456789abcdef flash length[ms] 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 90 ftim_dim(hex)101112131415161718191a1b1c1d1e1f flash length[ms] 110 130 150 170 190 210 230 250 270 290 310 330 350 370 390 410 table 14. aux led register aux_reg (write mode) msb lsb sub add = 02 auxi_3 auxi_2 auxi_1 auxi_0 auxt_3 auxt_2 auxt_1 auxt_0 power-on, shutdown mode reset value 00000000 table 15. auxiliary led dimming table auxi (hex) 0123456789ab aux led current [ma] 0 6 10 15 20 25 33 40 53 67 80 100
description of the internal registers stcf04 26/43 doc id 022927 rev 3 9.4 status (stat_reg) 03(hex) f_run : this bit is kept high by the stcf04 during flash mode. by checking this bit, the microprocessor can verify if the flash mode is running or has been terminated by the time counter. fl_r : (flash ready) this bit is set to 0 if the supercap voltage is not high enough to make a flash. ntc_w : this bit is set high by the stcf04 and the atn pin is pulled down, when the voltage seen on the pin r x exceeds v ref4 = 0.56 v. this threshold corresponds to a warning temperature value at the led measured by the ntc. the device is still operating, but a warning is sent to the microprocessor. this bit stays high until the temperature goes below the threshold. ntc_h : this bit is set high by the stcf04 and the atn pin is pulled down, when the voltage seen on the pin r x exceeds v ref5 = 1.2 v. this threshold corresponds to an excess temperature value at the led measured by the ntc. the device is put into idle mode to avoid damaging the led. this bit is reset by the stcf04 following a read operation of the stat_reg. ot_f : this bit is set high by the stcf04 and the atn pin is pulled down, when the chip overtemperature protection (~140 c) has put the device into idle mode. this bit is reset by the stcf04 following a read operation of the stat_reg. fl_ovr : this bit is set high, if the flash operation is terminated by the light sensor. lth : this bit is set high when the local temperature protection for the supercap charging circuit is activated. table 16. auxiliary led timing table auxt (hex)0123456789abcdef aux led time [s] 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 table 17. status register stat_reg (read mode) msb lsb sub add=03 n/a f_run fl_r ntc_w ntc_h ot_f fl_ovr lth power-on, shutdown mode reset value 0000000 0
stcf04 description of the internal registers doc id 022927 rev 3 27/43 9.5 feature (ftr_reg) 04(hex) ls_0~2 : these 3 bits define the value of the internal reference voltage for the light sensor comparator. the en_ls bit must be set to 1 to activate the internal reference for the light sensor comparator. en_ls : this bit enables the light sensor function when set high. vdc_0~1 : these 2 bits define the output voltage of the dc-dc converter. note: see section 10.4 . idc_0 : this bit defines the peak current limit value of the dc-dc converter. table 18. status register details bit name f_run (stat_reg) fl_r ntc_w (stat_reg) ntc_h (stat_reg) ot_f (stat_reg) fl_ovr lth default value 0 0 0 0 0 0 0 latched (1) no no yes yes yes no no forces idle mode when set no no no yes yes no no sets atn low when set no yes yes yes yes yes no 1. yes means that the bit is set by internal signals and is re set to default by an i2c read operation of stat_reg. no means that the bit is set and reset by internal signals in real-time. table 19. feature register ls_reg (write mode) msb lsb sub add=04 idc_0 n/a vdc_1 vdc_0 en_ls ls_2 ls_1 ls_0 power-on, shutdown mode reset value 00000000 table 20. light sensor reference dimming register settings ls_dim(hex) 0123 4 5 6 7 lsref[mv] 200 400 600 800 1000 1200 1400 1600 table 21. dc-dc converter output voltages (v out ) vdc_1 vdc_0 v out 004.5 v 015.0 v 105.5 v
description of the internal registers stcf04 28/43 doc id 022927 rev 3 9.6 torch register (trch_reg) 05(hex) ttrch_0~1 : these bits define the torch mode time. tdim_0~3 : these 4 bits define the led current in torch mode with 12 values. table 22. dc-dc converter coil peak current limit values idc_0 i coil (peak) 01.45 a 11.80 a table 23. torch register vrid_reg (read mode) msb lsb sub add=05 ttrch1 ttrch0 tdim_3 tdim_2 tdim_1 tdim_0 n/a n/a power-on, shutdown mode reset value 0000000 0 table 24. torch mode dimming registers settings tdim (hex) 0123456789ab led current [ma] 15 20 30 45 60 75 100 120 160 200 240 320 internal step 1 2 3 4 5 6 7 8 9 10 11 12 table 25. the safety timeout for torch mode ttrch1 ttrch0 torch time 0 0 infinity 01 5s 10 10s 11 15s
stcf04 theory of operation doc id 022927 rev 3 29/43 10 theory of operation 10.1 the state machine diagram the state machine diagram of the device describes the overall function of the logic part of the device. it helps with the understanding of all the working modes of the complex and efficient management of the stored energy. figure 13. state machine diagram of the stcf04 ! pwr_on & montr battery plu g -in idle fla s h + chrg + ntc torch + chrg + ntc chrg aux led on ntc chrg || fla s h_on || tch_on ntc fla s h_on &ready& l s tch_on & ready &tchv_h m a xtimefl as h ! tch_on m a xtimeled ! ntc & pwr_on !chrg || (ready &!fla s h_on & !tch_on) a u xled_on lock alarm from a ny s t a te s s t a t us _regi s ter re a d s h u tdown pwr_on !pwr_on || !re s et from a ny s t a te s monitorin g ! pwr_on & ntc ! pwr_on || ! montr ! pwr_on & ! ntc fla s h + chrg + ntc + l s fla s h_on & ready torch eff. + chrg + ntc tch_on &ready &!tchv_h pwr_on = power on montr = monitoring on l s _on = light s en s or on chrg = ch a rging on fla s h_on = b it fl as h_on & pin fl as h on tch_on = b it tch_on & pin torch on auxled_on = a u xili a ry led on ready = re a dy pin am11887v1
theory of operation stcf04 30/43 doc id 022927 rev 3 10.2 power-on reset this mode is initiated by applying a supply voltage above the v pw_on reset threshold value. an internal timing (~1 s) defines the duration of this status. the logic blocks are powered, but the device doesn't respond to any input. the registers are reset to their default values, the atn and sda pins are in high-z, and the i2c slave address is internally set by reading the add pin configuration. after the internally defined time has elapsed, the stcf04 automatically enters shutdown mode. for the additional reset of the device, it is also possible to use the reset pin. 10.2.1 reset pin function the device is put into reset mode when the logic level on the reset pin is 0. the logic blocks are powered, but the device doesn't respond to any input. the registers are reset to their default values; the atn and sda pins are in high-z. the reset pin must stay in low level for t resmin time (1 s) at least to guarantee correct resetting of the device. when the reset function driven by the reset pin is not needed, the reset pin must be connected to the v bat = v in . figure 14. reset timing 10.3 shutdown mode and ntc mode in shutdown mode only the i2c interface is live, accepting i2c commands and register settings. the device enters this mode automatically after reset or by resetting the pwr_on bit from other operation modes. power consumption is at the minimum (1 a typ.), if ntc is not activated (ntc_on = 0). if the ntc_on is set, the p can measure the led temperature through an a/d converter connected to the ntc pin. when ntc circuits are active and the v ref-ext is present, the typical current consumption is increased to 2 a. it is recommended to not leave the stcf04 in this status if battery drain must be minimized. 10.4 monitoring mode when the vdc voltage set by the ftr_reg is not 0, the comparator of the supercap voltage is live. this comparator checks the voltage on the supercap continuously. if it is higher than the v supmax threshold, then the ready pin is pulled low and stays low until the voltage on the supercap is higher than v supmax - 200 mv.
stcf04 theory of operation doc id 022927 rev 3 31/43 10.5 idle mode in this mode all internal blocks are turned on. the dc-dc converter can be enabled by setting the chrg bit to 1. if it is enabled, the supercap is automatically charged. the ntc circuit can be activated to monitor the temperature of the led and i2c commands and register settings are allowed to be executed immediately. the device enters this mode: from monitoring when setting the pwr_on bit from flash operation by resetting the flash pin or the flash_on bit, or automatically from flash operation when the time counter reaches zero from torch operation by resetting the tch_on bit. the device automatically enters this mode also when an overload or an abnormal condition has been detected during flash or torch operation (see ta b l e 1 7 ). 10.6 aux led the stcf04 is capable of driving an auxiliary led. its cathode is always connected to the auxled pin, while its anode can be connected either to the v bat or v out pin. connecting it to the v out pin is particularly advantageous in case of high auxled currents. the maximum values of auxled currents are guaranteed only for anode voltages higher than 3.3 v, but v bat may range from 2.7 v to 5.5 v, so in some cases it may not be possible to use maximum currents. 10.7 single or multiple flash using external (microprocessor) temporization to avoid the i2c bus time latency, it is recommended to use the dedicated flash pin to define the flash duration (hard-triggering). the flash_on bit of cmd_reg should be set before starting each flash operation, because it may have been reset automatically in the previous flash operation. the flash duration is determined by the pulse length that drives the flash pin. as soon as the flash is activated, the system needs typically 0.3 ms to ramp up the output current on the power led. the internal time counter times out flash operation and keeps the led dissipated energy within safe limits in case of software deadlock; the ftim register must be set first. multiple flashes are possible by strobing the flash pin. the timeout counter cumulates every flash on-time until the defined timeout is reached unless it is reloaded by updating the cmd_reg. the number of the flashes depends on v fled , when the supercap is discharged down to 4.2 v, the device goes automatically into idle mode. after a flash operation is timed out, the device automatically enters idle mode by resetting the flash_on bit, and it also resets the f_run bit. the atn pin is pulled down to inform the microprocessor that the stat_reg has been updated. multiple flash is possible to trigger as long as the ready pin is low.
theory of operation stcf04 32/43 doc id 022927 rev 3 10.8 external (microprocessor) temporization using the flash_on bit even though it is possible, it is not recommended to use the flash_on bit to start and stop the flash operation, because of i2c bus latencies: this may result in inaccurate flash timing. nevertheless, if this operation mode is chosen, the flash pin must be kept high (logic level or wired to v bat ), leaving the whole flash control to the i2c bus. also in this operation mode the time counter times out flash operation and keeps the energy dissipated by the led within safe limits in case of software deadlock. 10.9 single flash using internal temporization flash triggering can be obtained either by the flash pin (hard-triggering) or by i2c commands (soft-triggering). the first solution is recommended for an accurate start time, while the second is less accurate because of the i2c bus time latency. stop time is defined by the stcf04 internal temporization and its accuracy is determined by the internal oscillator. for hard-triggering, it is necessary to set the flash_on bit in advance. for soft- triggering, the flash pin must be kept high (logic level or wired to v bat ) and the flash can be started by setting the ftim and the trig_en through i2c (both are located in the cmd reg). there is a delay time between the moment the flash is triggered and when it appears. this delay is caused by the time necessary to charge up the output capacitor, which depends on battery voltage. once triggered, the flash operation is stopped when the time counter reaches zero. as soon as the flash is finished, the f_run bit is reset, the atn pin is pulled down for 11 s to inform the microprocessor that the stat_reg has been updated and the device goes back to idle mode. 10.10 light sensor feature this function works as an optional feature, which is able to optimize the length of the flash according to the light conditions in the flashed area. it uses an external capacitor c int , which is charged by a current coming from the external voltage reference, which is limited by the light sensor (generally made by a phototransistor). before the start of the flash operation, the c int capacitor is discharged by the internal switch to the zero voltage during 200 s. during the flash operation the c int capacitor integrates the charging current according to the light conditions in the flashed area. when the voltage level on the c int capacitor reaches the internal reference voltage, which is set by the light sensor register (r4, ls_0~2), the stcf04 stops the operation of the flash and discharges the c int capacitor through an internal switch.
stcf04 typical performance characteristics doc id 022927 rev 3 33/43 11 typical performance characteristics figure 15. flash current vs. input voltage figure 16. torch current vs. input voltage 0 0,5 1 1,5 2 2,5 3 3 ,5 4 4,5 5 5,5 6 6,5 7 7,5 8 2,25 2,5 2,75 33 ,25 3 ,5 3 ,75 4 4,25 4,5 4,75 v in [v] i out [a] i out = 1.2 a i out = 4. 8 a i out = 8 a am09 3 07v1 0 25 50 75 100 125 150 175 200 225 250 275 3 00 3 25 3 50 2,25 2,5 2,75 33 ,25 3 ,5 3 ,75 4 4,25 4,5 4,75 v in [v] i out [ma] i out = 3 20 ma i out = 160 ma i out = 40 ma am09 3 0 8 v1
typical performance characteristics stcf04 34/43 doc id 022927 rev 3 figure 17. aux led current vs. input voltage figure 18. charging efficiency vs. v out voltage (v in = 3.6 v) i out [ma] 0 5 10 15 20 25 3 0 3 5 40 45 50 55 60 65 70 75 8 0 8 5 90 95 100 105 110 2,25 2,5 2,75 33 ,25 3 ,5 3 ,75 4 4,25 4,5 4,75 v in [v] i out = 10 ma i out = 100 ma am09 3 09v1 am09 3 10v1 0 10 20 3 0 40 50 60 70 8 0 90 100 012 3 456 v out [v] eff. [%]
stcf04 typical performance characteristics doc id 022927 rev 3 35/43 figure 19. torch time - settings compared to real values figure 20. torch current - settings compared to real values figure 21. flash time - settings compared to real values am09 3 11v1 0 2 4 6 8 10 12 14 16 12 3 45 s tep time [ s ] time me asu red time s et am09 3 12v1 0 50 100 150 200 250 3 00 3 50 0246 8 10 12 14 s tep i out [ma] i out me asu red i out s et 0 50 100 150 200 250 3 00 3 50 400 450 0 5 10 15 20 25 3 0 3 5 s tep time [m s ] time me asu red time s et am09 3 1 3 v1
typical performance characteristics stcf04 36/43 doc id 022927 rev 3 figure 22. flash current - settings compared to real values figure 23. aux led time - settings compared to real values figure 24. aux led current- settings compared to real values 0 2 4 6 8 10 12 14 0246 8 10 s tep i out [a] i out me asu red i out s et am09 3 14v1 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 051015 s tep time [ s ] time me asu red time s et am09 3 15v1 am09 3 16v1 0 20 40 60 8 0 100 120 02 46 8 10 12 s tep i out [ma] i out me asu red i out s et
stcf04 typical performance characteristics doc id 022927 rev 3 37/43 figure 25. operation in flash mode - single flash pulse blue - supercap voltage; green - led current; magenta - flash pin; figure 26. operation in flash mode - multiple flash pulses blue - supercap voltage; green - led current; magenta - battery current;
typical performance characteristics stcf04 38/43 doc id 022927 rev 3 figure 27. operation in torch mode with tchv_h bit = 0 blue - supercap voltage; green - led current; magenta - battery current; figure 28. operation in torch mode with tchv_h bit = 1 blue - supercap voltage; green - led current; magenta - battery current.
stcf04 package mechanical data doc id 022927 rev 3 39/43 12 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions and product status are available at: www.st.com. ecopack is an st trademark.
package mechanical data stcf04 40/43 doc id 022927 rev 3 dim. mm. mil s . min. typ. max. min. typ. max. a 1.0 1.1 1.16 39 .4 4 3 . 3 45.7 a1 0.25 9 . 8 a2 0.7 8 0. 8 6 3 0.7 33 . 9 b 0.25 0. 3 00. 3 5 9 . 8 11. 8 1 3 . 8 d2. 93 .0 3 .1 114.2 11 8 .1 122.0 d1 2 7 8 . 8 e2. 93 .0 3 .1 114.2 11 8 .1 122.0 e1 2 7 8 . 8 e0.5 1 9 .7 s e 0.25 9 . 8 tfbga25 mechanical data 75 399 7 9 /a
stcf04 package mechanical data doc id 022927 rev 3 41/43 dim. mm. inch. min. typ. max. min. typ. max. a 33 0 12. 99 2 c 12. 8 1 3 .2 0.504 0.51 9 d 20.2 0.7 9 5 n60 2. 3 62 t 14.4 0.567 ao 3 . 3 0.1 3 0 bo 3 . 3 0.1 3 0 ko 1.60 0.06 3 po 3 . 9 4.1 0.15 3 0.161 p7. 98 .1 0. 3 11 0. 3 1 9 tape & reel tfbga25 mechanical data
revision history stcf04 42/43 doc id 022927 rev 3 13 revision history table 26. document revision history date revision changes 14-mar-2012 1 initial release. 16-may-2012 2 document status promoted from preliminary data to production data. 13-sep-2012 3 modified: t fl value 12 m table 5 on page 11 .
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